A FLEXIBLE SHARED-BUFFER SWITCH FOR ATM AT GB/S RATES

This paper presents the architecture of a very high-speed VLSI packet switch and its performance. The switch, called PRIZMA, is suited for broadband telecommunications, based on ATM, the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. There may be applications within private networks, independent of whether they are ATM-based. There may also be other potential applications such as multiprocessor interconnection. The architecture of the PRIZMA switch follows the architecture of its lower-speed earlier version (H. Ahmadi et al., Int. J. Digital Analog Cabled Syst. 2 (4) (1989) 277-287) to a large degree: It is based on a single-chip switch element that exploits the performance advantage of output queuing and from which larger, self-routing single-stage or multistage switch fabrics can be constructed in a modular way. However, compared to the precursor, higher performance is achieved by output queues that now are configured as a dynamically shared memory. This shared memory can also be expanded by linking multiple switch elements. Owing to novel parallel structures inside the switch element, VLSI implementation is possible for transmission rates on the order of a gigabit per second per port. In the last section of this paper, performance results are presented for a switch in a single-stage configuration as well as for the case of a three-stage switch fabric.