A Low Power L1 Cache Design Based on Data and Tag Re-Mapping

In this work, we propose an architecture-level power optimization technique for L1 caches. The idea is to unify the DATA and TAG fields in a unique embedded static RAM and an intelligent cache controller to minimize the latency penalty. Moreover, an intermediate high-speed pre-fetch buffer optimizes the whole system. We apply this approach to direct-mapped instruction cache and set-associative data cache. Experimental results indicate the power saving by 20% with latency overhead by 12%.