A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE

被引：80
|
作者：
HARATA, Y [1 ]
NAKAMURA, Y [1 ]
NAGASE, H [1 ]
TAKIGAWA, M [1 ]
TAKAGI, N [1 ]
机构：
[1] KYOTO UNIV,FAC ENGN,DEPT INFORMAT SCI,KYOTO 606,JAPAN
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 01期
关键词：
D O I：
10.1109/JSSC.1987.1052667
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：28 / 34
页数：7
相关论文
共 50 条
  • [1] A High-Speed Booth Multiplier Based on Redundant Binary Algorithm
    Barik, Ranjan Kumar
    Panda, Ashish
    Pradhan, Manoranjan
    [J]. PROGRESS IN ADVANCED COMPUTING AND INTELLIGENT ENGINEERING, VOL 2, 2018, 564 : 569 - 575
  • [2] HIGH-SPEED BINARY ADDER
    LING, H
    [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1981, 25 (2-3) : 156 - 166
  • [3] HIGH-SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION AND THEIR IMPLEMENTATION IN A MICROPROCESSOR
    KUNINOBU, S
    NISHIYAMA, T
    TANIGUCHI, T
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1993, E76C (03) : 436 - 445
  • [4] HIGH-SPEED BINARY MULTIPLIER
    KINGSBUR.NG
    [J]. ELECTRONICS LETTERS, 1971, 7 (10) : 277 - &
  • [5] HIGH-SPEED VLSI MULTIPLICATION ALGORITHM WITH A REDUNDANT BINARY ADDITION TREE
    TAKAGI, N
    YASUURA, H
    YAJIMA, S
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1985, 34 (09) : 789 - 796
  • [6] High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation
    Thamizharasan, V.
    Kasthuri, N.
    [J]. IETE JOURNAL OF RESEARCH, 2023, 69 (05) : 2301 - 2309
  • [7] GaAs multiplier and adder designs for high-speed DSP applications
    Beaumont-Smith, A
    Burgess, N
    Cui, S
    Liebelt, M
    [J]. THIRTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1517 - 1521
  • [8] Novel high-speed redundant binary to binary converter using prefix networks
    Veeramachaneni, Sreehari
    Krishna, M. Kirthi
    Avinash, Lingamneni
    Reddy, Sreekanth P.
    Srinivas, M. B.
    [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3271 - 3274
  • [9] HIGH-SPEED BINARY RATE-MULTIPLIER
    MAJITHIA, JC
    [J]. PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1972, 60 (03): : 339 - &
  • [10] HIGH-SPEED BINARY RATE-MULTIPLIER
    ELLIOTT, AR
    [J]. PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1971, 59 (08): : 1256 - &
12345