A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE

A 16-bit multiplied by 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2. 7- mu m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log//2 n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit multiplied by 16-bit multiplier chip size is 5. 8 multiplied by 6. 3 mm**2 using the new layout for a binary adder tree. The chip contains about 10,600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit multiplied by 32-bit multiplication time is about 140 ns.