A 100-MHZ 2-D 8X8 DCT/IDCT PROCESSOR FOR HDTV APPLICATIONS

被引：102

作者：

MADISETTI, A

WILLSON, AN

机构：

[1] Integrated Circuits and Systems Laboratory, Department of Electrical Engineering, University of California, Los Angeles

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1995年 / 5卷 / 02期

关键词：

D O I：

10.1109/76.388064

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8 x 8 blocks, Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation, Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT, The layout has been generated with a 0.8 mu m CMOS library using the Mentor Graphics GDT tools and measures under 10 mm(2). Critical path simulation indicates a maximum input sample rate of 100 MHz.

引用

页码：158 / 165

页数：8

共 50 条

[31] A Low Power 8 x 8 Direct 2-D DCT Chip Design
Hao-Chieh Chang
Jiun-Ying Jiu
Li-Lin Chen
Liang-Gee Chen
[J]. Journal of VLSI signal processing systems for signal, image and video technology, 2000, 26 : 319 - 332
[32] VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
Srinivasan, V
Liu, KJR
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1996, 6 (01) : 87 - 96
[33] A new fast algorithm for 8 x 8 2-D DCT and its VLSI implementation
Tian, M
Li, GJ
Peng, QZ
[J]. PROCEEDINGS OF 2005 IEEE INTERNATIONAL WORKSHOP ON VLSI DESIGN AND VIDEO TECHNOLOGY, 2005, : 179 - 182
[34] Computation of 2D 8x8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding
Coelho, Diego F. G.
Nimmalapalli, Sushmabhargavi
Dimitrov, Vassil S.
Madanayake, Arjuna
Cintra, Renato J.
Tisserand, Arnaud
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (12) : 1692 - 1702
[35] Multiplication-free 8x8 2D DCT architecture using algebraic integer encoding
Dimitrov, V
Wahid, K
Jullien, G
[J]. ELECTRONICS LETTERS, 2004, 40 (20) : 1310 - 1311
[36] Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8x8 2D-IDCT architecture
Kim, S
Sung, WY
[J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 672 - 675
[37] Fixed-point error analysis and wordlength optimization of a distributed arithmetic based 8x8 2D-IDCT architecture
Kim, S
Sung, W
[J]. VLSI SIGNAL PROCESSING, IX, 1996, : 398 - 407
[38] A 600MHz 2D-DCT processor for MPEG applications
Sarmiento, R
Pulido, C
Tobajas, F
Armas, V
Esper-Chain, R
Lopez, J
Montiel-Nelson, J
Nunez, A
[J]. THIRTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1527 - 1531
[39] Self-routing in 2-D shuffle networks with dimension-independent switches of size ≥8x8
Giglmayr, J
[J]. PARALLEL COMPUTING: FUNDAMENTALS, APPLICATIONS AND NEW DIRECTIONS, 1998, 12 : 445 - 449
[40] RNS-based implementation of 8x8 point 2D-DCT over field-programmable devices
Fernández, PG
Lloris, A
[J]. ELECTRONICS LETTERS, 2003, 39 (01) : 21 - 23

← 1 2 3 4 5 →