RNS-based implementation of 8x8 point 2D-DCT over field-programmable devices

被引：20
|
作者：
Fernández, PG [1 ]
Lloris, A [1 ]
机构：
[1] Dept Electron & Tecnol Computadores, Granada 18071, Spain
来源：
ELECTRONICS LETTERS | 2003年 / 39卷 / 01期
关键词：
D O I：
10.1049/el:20030084
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new implementation of an 8 x 8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.
引用
收藏
页码：21 / 23
页数：3
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