Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8x8 2D-IDCT architecture

被引：0
|
作者：
Kim, S [1 ]
Sung, WY [1 ]
机构：
[1] SEOUL NATL UNIV,SCH ELECT ENGN,SEOUL 151,SOUTH KOREA
来源：
ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2 | 1996年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
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页码：672 / 675
页数：4
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