A 100-MHZ 2-D 8X8 DCT/IDCT PROCESSOR FOR HDTV APPLICATIONS

被引：102
|
作者：
MADISETTI, A
WILLSON, AN
机构：
[1] Integrated Circuits and Systems Laboratory, Department of Electrical Engineering, University of California, Los Angeles
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1995年 / 5卷 / 02期
关键词：
D O I：
10.1109/76.388064
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8 x 8 blocks, Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation, Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT, The layout has been generated with a 0.8 mu m CMOS library using the Mentor Graphics GDT tools and measures under 10 mm(2). Critical path simulation indicates a maximum input sample rate of 100 MHz.
引用
收藏
页码：158 / 165
页数：8
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