A 200-MHZ 64-B DUAL-ISSUE CMOS MICROPROCESSOR

被引：109

作者：

DOBBERPUHL, DW

WITEK, RT

ALLMON, R

ANGLIN, R

BERTUCCI, D

BRITTON, S

CHAO, L

CONRAD, RA

DEVER, DE

GIESEKE, B

HASSOUN, SMN

HOEPPNER, GW

KUCHLER, K

LADD, M

LEARY, BM

MADDEN, L

MCLELLAN, EJ

MEYER, DR

MONTANARO, J

PRIORE, DA

RAJAGOPALAN, V

SAMUDRALA, S

SANTHANAM, S

机构：

[1] Semiconductor Engineering Group, Digital Equipment Corporation, Hudson

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 11期

关键词：

D O I：

10.1109/4.165336

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75-mum CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm x 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation.

引用

页码：1555 / 1567

页数：13

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