HAZARD CORRECTION IN SYNCHRONOUS SEQUENTIAL CIRCUITS

被引：0
|
作者：
SERVIT, M [1 ]
机构：
[1] CZECHOSLOVAK POLYTECH INST, ELECTROTECH FAC, DEPT COMP, PRAGUE, CZECHOSLOVAKIA
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1975年 / C 24卷 / 03期
关键词：
D O I：
10.1109/T-C.1975.224211
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：305 / 310
页数：6
相关论文
共 50 条
  • [31] Deriving approximate circuits for TMR technique applied to synchronous sequential circuits
    Ostanin, Sergey A.
    Matrosova, Angela Yu
    Andreeva, Valentina V.
    [J]. VESTNIK TOMSKOGO GOSUDARSTVENNOGO UNIVERSITETA-UPRAVLENIE VYCHISLITELNAJA TEHNIKA I INFORMATIKA-TOMSK STATE UNIVERSITY JOURNAL OF CONTROL AND COMPUTER SCIENCE, 2023, (62): : 124 - 131
  • [32] On static compaction of test sequences for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. 33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 215 - 220
  • [33] MIX: A test generation system for synchronous sequential circuits
    Lin, XJ
    Pomeranz, I
    Reddy, SM
    [J]. ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 456 - 463
  • [34] Templates: A test generation procedure for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 74 - 79
  • [35] Modified test generation methods for synchronous sequential circuits
    Kemamalini, A.
    Seshasayanan, R.
    [J]. 2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [36] Invariant states and redundant logic in synchronous sequential circuits
    Pomeranz, Irith
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (06) : 1171 - 1175
  • [37] INTEGRATED MAGNETIC CIRCUITS FOR SYNCHRONOUS SEQUENTIAL LOGIC MACHINES
    GIANOLA, UF
    [J]. BELL SYSTEM TECHNICAL JOURNAL, 1960, 39 (02): : 295 - 332
  • [38] An efficient test relaxation technique for synchronous sequential circuits
    El-Maleh, A
    Al-Utaibi, K
    [J]. 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 179 - 185
  • [39] Ant Colony Optimizations for Initialization of synchronous sequential circuits
    Hu, Xiaojing
    Song, Zhengxiang
    Wang, Jianhua
    Geng, Yingsan
    Shen, Wang
    [J]. IEEE CIRCUITS AND SYSTEMS INTERNATIONAL CONFERENCE ON TESTING AND DIAGNOSIS, 2009, : 424 - 427
  • [40] Accelerating Synchronous Sequential Circuits using an Adaptive Clock
    Mondal, Arijit
    Chakrabarti, P. P.
    Dasgupta, Pallab
    [J]. 23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2010, : 176 - +
12345