THE NS32081 FLOATING-POINT UNIT - ARCHITECTURE AND IMPLEMENTATION

The NS32081 floating-point unit, an NMOS processor that provides high-speed floating-point operations, is described. The NS32081 implements the core of the proposed IEEE standard for binary floating-point arithmetic, with an emphasis on fast execution. The remainder of the standard is supported by a software package. Thus, by mixing hardware and software implementation, both high performance and full compatibility with the proposed IEEE standard have been obtained while keeping the chip design relatively simple. Topics discussed include the slave processor concept, internal structure, parallel multiway-brand, microcode and logic circuit implementations.