Design and Implementation of a Reduced Floating-Point Reconfigurable Computing Unit

This paper presents a novel coarse-grained reconfigurable computing unit (RCU) with the advantages of simple architecture, convenient integration, multi-level reconfiguration, and dynamic reconfiguration for computing-intensive applications. Multiple RCUs can be composed into computing arrays to improve computational efficiency. The RCUs are integrated into a heterogeneous multi-core system (RHPS), which is organized in loose coupling integration based on NoC communication architecture. The total hardware prototype is implemented on Xilinx v6lx760ff1760-1 device and can work steadily at 120MHz. A three-layer software programming architecture is proposed based on the properties of the heterogeneous multi-core system and reconfigurable computing units, which simplifies the difficulty of programming greatly. Furthermore, as an instance, FIR filtering algorithm is mapped on RHPS system and lots of experiments are carried for performance evaluation. Experimental results prove the excellent parallel computing ability of RCU, and show a good linear relationship between the computation workload and the processing time. Furthermore, great performance increase can be achieved by improving application algorithm map, or simply widen the outside memory access bandwidth.