A 90NS 1MB DRAM WITH MULTI-BIT TEST MODE

被引：0
|
作者：
KUMANOYA, M
FUJISHIMA, K
TSUKAMOTO, K
NISHIMURA, Y
SAITO, K
MATSUKAWA, T
YOSHIHARA, T
NAKANO, T
机构：
来源：
ISSCC DIGEST OF TECHNICAL PAPERS | 1985年 / 28卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：240 / 241
页数：2
相关论文
共 50 条
  • [1] AN 85NS 1MB DRAM IN A PLASTIC DIP
    INOUE, Y
    MUROTANI, T
    FUKUZOH, Y
    HAYANO, K
    FUJII, T
    MINAMI, K
    NAKAMURA, K
    KIKUCHI, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 238 - 239
  • [2] A 1MB CMOS DRAM
    KIRSCH, HC
    CLEMONS, DG
    DAVAR, S
    HARMAN, JE
    HOLDER, CH
    HUNSICKER, WF
    PROCYK, FJ
    STEFANY, JH
    YANEY, DS
    PETRIZZI, JB
    IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, 1985, 28 : 256 - 257
  • [3] 1MB DRAM ALTERNATIVES
    CHOU, S
    CZEKALSKI, M
    GROWHOWSKI, CJ
    ITOH, K
    KIRSCH, HC
    MIYASAKA, K
    PENZEL, HJ
    ROSENZWEIG, W
    SEGERS, D
    ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 132 - 133
  • [4] A 20NS STATIC COLUMN 1MB DRAM IN CMOS TECHNOLOGY
    SATO, K
    KAWAMOTO, H
    YANAGISAWA, K
    MATSUMOTO, T
    SHIMIZU, S
    HORI, R
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 254 - 255
  • [5] AN EXPERIMENTAL 80NS 1MB DRAM WITH FAST PAGE OPERATION
    KALTER, HL
    COPPENS, P
    ELLIS, W
    FIFIELD, J
    KOKOSZKA, D
    LEASURE, T
    MILLER, C
    NGUYEN, Q
    PAPRITZ, R
    PATTON, C
    POPLAWSKI, M
    TOMASHOT, S
    VANDERHOEVEN, V
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 248 - 249
  • [6] 采用双层A1工艺的90ns 256k×1位DRAM
    Takeo Fujii
    李儒章
    微电子学, 1985, (Z1) : 196 - 198
  • [7] AN 80NS 1MB ROM
    MASUOKA, F
    ARIIZUMI, S
    IWASE, T
    ONO, M
    ENDO, N
    ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 146 - &
  • [8] A RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE
    KUMANOYA, M
    FUJISHIMA, K
    MIYATAKE, H
    NISHIMURA, Y
    SAITO, K
    MATSUKAWA, T
    YOSHIHARA, T
    NAKANO, T
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) : 909 - 913
  • [9] A 1MB DRAM WITH A FOLDED CAPACITOR CELL STRUCTURE
    HORIGUCHI, F
    ITOH, Y
    IIZUKA, H
    OGURA, M
    MASUOKA, F
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 244 - 245
  • [10] A 1MB CMOS DRAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE
    TAYLOR, R
    JOHNSON, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 242 - 243
12345