A 1MB DRAM WITH A FOLDED CAPACITOR CELL STRUCTURE

被引：0
|
作者：
HORIGUCHI, F [1 ]
ITOH, Y [1 ]
IIZUKA, H [1 ]
OGURA, M [1 ]
MASUOKA, F [1 ]
机构：
[1] TOSHIBA CORP,DIV IC,KAWASAKI 210,JAPAN
来源：
ISSCC DIGEST OF TECHNICAL PAPERS | 1985年 / 28卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：244 / 245
页数：2
相关论文
共 50 条
  • [1] A 1MB CMOS DRAM
    KIRSCH, HC
    CLEMONS, DG
    DAVAR, S
    HARMAN, JE
    HOLDER, CH
    HUNSICKER, WF
    PROCYK, FJ
    STEFANY, JH
    YANEY, DS
    PETRIZZI, JB
    IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, 1985, 28 : 256 - 257
  • [2] 1MB DRAM ALTERNATIVES
    CHOU, S
    CZEKALSKI, M
    GROWHOWSKI, CJ
    ITOH, K
    KIRSCH, HC
    MIYASAKA, K
    PENZEL, HJ
    ROSENZWEIG, W
    SEGERS, D
    ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 132 - 133
  • [3] A 1MB DRAM WITH 3-DIMENSIONAL STACKED CAPACITOR CELLS
    TAKEMAE, Y
    EMA, T
    NAKANO, M
    BABA, F
    YABU, T
    MIYASAKA, K
    SHIRAI, K
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 250 - 251
  • [4] AN 85NS 1MB DRAM IN A PLASTIC DIP
    INOUE, Y
    MUROTANI, T
    FUKUZOH, Y
    HAYANO, K
    FUJII, T
    MINAMI, K
    NAKAMURA, K
    KIKUCHI, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 238 - 239
  • [5] A 1MB CMOS DRAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE
    TAYLOR, R
    JOHNSON, M
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 242 - 243
  • [6] AN EXPERIMENTAL 1MB DRAM WITH ON-CHIP VOLTAGE LIMITER
    ITOH, K
    HORI, R
    ETOH, J
    ASAI, S
    HASHIMOTO, N
    YAGI, K
    SUNAMI, H
    ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 282 - 283
  • [7] Capacitor structure for a 1 Gbit DRAM cell
    Mann, D
    ELECTRONIC ENGINEERING, 1996, 68 (834): : 68 - 68
  • [8] A 1MB CMOS DRAM WITH FAST PAGE AND STATIC COLUMN MODES
    SAITO, S
    FUJII, S
    OKADA, Y
    SAWADA, S
    SHINOZAKI, S
    NATORI, K
    OZAWA, O
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 252 - 252
  • [9] A 20NS STATIC COLUMN 1MB DRAM IN CMOS TECHNOLOGY
    SATO, K
    KAWAMOTO, H
    YANAGISAWA, K
    MATSUMOTO, T
    SHIMIZU, S
    HORI, R
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 254 - 255
  • [10] AN EXPERIMENTAL 80NS 1MB DRAM WITH FAST PAGE OPERATION
    KALTER, HL
    COPPENS, P
    ELLIS, W
    FIFIELD, J
    KOKOSZKA, D
    LEASURE, T
    MILLER, C
    NGUYEN, Q
    PAPRITZ, R
    PATTON, C
    POPLAWSKI, M
    TOMASHOT, S
    VANDERHOEVEN, V
    ISSCC DIGEST OF TECHNICAL PAPERS, 1985, 28 : 248 - 249
12345