A 1MB DRAM WITH A FOLDED CAPACITOR CELL STRUCTURE

被引：0
|
作者：
HORIGUCHI, F [1 ]
ITOH, Y [1 ]
IIZUKA, H [1 ]
OGURA, M [1 ]
MASUOKA, F [1 ]
机构：
[1] TOSHIBA CORP,DIV IC,KAWASAKI 210,JAPAN
来源：
ISSCC DIGEST OF TECHNICAL PAPERS | 1985年 / 28卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：244 / 245
页数：2
相关论文
共 50 条
  • [41] SIEMENS JOINS THE 1-MB DRAM CLUB
    GOSCH, J
    ELECTRONICS, 1986, 59 (35): : 30 - 31
  • [42] A NOVEL CAPACITOR-LESS DRAM WITH RAISED SOURCE STRUCTURE
    Lu, Dai-Rong
    Lin, Jyi-Tsong
    Tseng, Shih-Chuan
    Lin, Po-Hsieh
    Huang, Zih-Hao
    Syu, Jyun-Min
    Wang, Yu-Chun
    Lin, Yong-Huang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [43] 缓存之争1MB比512KB强多少
    姑苏飘雪
    现代计算机(普及版), 2006, (04) : 114 - 115
  • [44] Capacitor-less 1-Transistor DRAM
    Fazan, P
    Okhonin, S
    Nagoga, M
    Sallese, JM
    Portmann, L
    Ferrant, R
    Kayal, M
    Pastre, M
    Blagojevic, M
    Borschberg, A
    Declercq, M
    2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 10 - 13
  • [45] 世界最高速的1Mb字段存储器
    吴茂林
    电子技术, 1988, (12) : 16 - 16
  • [46] A fully printable, self-aligned and planarized stacked capacitor DRAM cell technology for 1Gbit DRAM and beyond
    Kohyama, Y
    Ozaki, T
    Yoshida, S
    Ishibashi, Y
    Nitta, H
    Inoue, S
    Nakamura, K
    Aoyama, T
    Imai, K
    Hayasaka, N
    1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 17 - 18
  • [47] Efficient screening method for DRAM memory cell capacitor dielectric
    Furutani, Kiyohiro
    Suwa, Makoto
    Arimoto, Kazutami
    Mashiko, Koichiro
    Yamada, Michihiro
    Matsumoto, Masatoshi
    Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1990, 73 (11): : 81 - 89
  • [48] A HIGH-PERFORMANCE 1-MBIT DYNAMIC RAM WITH A FOLDED CAPACITOR CELL
    HORIGUCHI, F
    OGURA, M
    WATANABE, S
    SAKUI, K
    MIYAWAKI, N
    ITOH, Y
    KUROSAWA, K
    MASUOKA, F
    IIZUKA, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) : 1076 - 1081
  • [49] New modeling method for the dielectric relaxation of a DRAM cell capacitor
    Choi, Sujin
    Sun, Wookyung
    Shin, Hyungsoon
    SOLID-STATE ELECTRONICS, 2018, 140 : 29 - 33
  • [50] 用铜导体连接技术的1Mb MRAM问世
    电子设计技术, 2002, (08) : 44 - 44
12345