A LOW-POWER BIPOLAR ECL STANDARD CELL LIBRARY UTILIZING A NOVEL DESIGN METHODOLOGY AND COMPLEMENTARY BIPOLAR DRIVER

被引：0
|
作者：
PHAM, P
KAWAMOTO, E
DAVIS, G
SPANGLER, L
机构：
来源：
PROCEEDINGS OF THE 1989 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING | 1989年
关键词：
D O I：
10.1109/BIPOL.1989.69452
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：19 / 22
页数：4
相关论文
共 50 条
  • [1] BIPOLAR PROCESS YIELDS LOW-POWER ECL
    BURSKY, D
    ELECTRONIC DESIGN, 1989, 37 (04) : 37 - 38
  • [2] CREATING LOW-POWER BIPOLAR ECL AT VLSI DENSITIES
    WILSON, G
    VLSI SYSTEMS DESIGN, 1986, 7 (05): : 84 - 86
  • [3] High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing
    Koike, K
    Kawai, K
    Onozawa, A
    Takei, Y
    Kobayashi, Y
    Ichino, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (10) : 1536 - 1544
  • [4] Low-Power Design Methodology for CML and ECL Circuits
    Schrape, Oliver
    Appel, Markus
    Winkler, Frank
    Krstic, Milos
    2014 24TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2014,
  • [5] A CAD-based low-power design methodology for very high-speed Si bipolar standard cell LSIs
    Koike, K
    Kawai, K
    Onozawa, A
    Takei, Y
    Kobayashi, Y
    Ichino, H
    IEICE TRANSACTIONS ON ELECTRONICS, 1997, E80C (12): : 1578 - 1585
  • [6] Novel methodology to determine leakage power in standard cell library design
    Charafeddine, Kenza
    Ouardi, Faissal
    HELIYON, 2020, 6 (06)
  • [7] Simulation and design of InGaAsN-based heterojunction bipolar transistors for complementary low-power applications
    Monier, C
    Chang, PC
    Li, NY
    LaRoche, JR
    Baca, AG
    Hou, HQ
    Ren, F
    Pearton, SJ
    SOLID-STATE ELECTRONICS, 2000, 44 (09) : 1515 - 1521
  • [8] The design of a standard cell library for low-power / low-voltage VLSI applications
    Wang, J.-S.
    Shieh, S.-J.
    Wang, J.-C.
    Yang, P.-H.
    Yeh, C.-W.
    Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an, 2001, 8 (02): : 119 - 132
  • [9] CMOS and bipolar novel low-power adaptive biasing topologies
    Universita Tor Vergata, Rome, Italy
    Microelectron J, 3 (223-227):
  • [10] CMOS and bipolar novel low-power adaptive biasing topologies
    Cardarilli, GC
    Ferri, G
    Re, M
    MICROELECTRONICS JOURNAL, 1999, 30 (03) : 223 - 227
12345