LATENCY COST AND ARCHITECTURE

被引:0
|
作者
SENZIG, DN
TUNG, C
PANIGRAHI, VG
RAU, BR
WENSLEY, JH
HOLLANDER, GL
机构
[1] HEWLETT PACKARD CO,SAN DIEGO,CA 92100
[2] IBM CORP,SAN DIEGO,CA
[3] BURROUGHS CORP,SAN DIEGO,CA
[4] STANFORD UNIV,STANFORD,CA
[5] STANFORD RES INST,STANFORD,CA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:8 / 10
页数:3
相关论文
共 50 条
  • [31] Effects of communication latency, overhead, and bandwidth in a cluster architecture
    Martin, RP
    Vahdat, AM
    Culler, DE
    Anderson, TE
    24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, CONFERENCE PROCEEDINGS, 1997, : 85 - 97
  • [32] A Case Study on NoC Router Architecture For Optimizing The Latency
    Ramani, S.
    Sundararajan, J.
    PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION SYSTEMS (ICACCS), 2013,
  • [33] Memory latency optimizations for the elementary functions on the Sunway architecture
    Zhou, Bei
    Huang, Yongzhong
    Xu, Jinchen
    Guo, Shaozhong
    Qi, Hongyuan
    JOURNAL OF SUPERCOMPUTING, 2019, 75 (07): : 3917 - 3944
  • [34] Improving Latency in a Signal Processing System on the Epiphany Architecture
    Brauer, Peter
    Lundqvist, Martin
    Mallo, Aare
    2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP), 2016, : 796 - 800
  • [35] A Latency-Efficient Router Architecture for CMP Systems
    Roca, Antoni
    Flich, Jose
    Silla, Federico
    Duato, Jose
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 165 - 172
  • [36] Multistage Latency Adders Architecture Employing Approximate Computing
    Yang, Xinghua
    Xing, Yue
    Qiao, Fei
    Yang, Huazhong
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (03)
  • [37] A Low Latency Decoder Architecture for Short Polar Codes
    Khalel, Mina
    Reggiani, Luca
    Ferrari, Riccardo
    2020 17TH BIENNIAL BALTIC ELECTRONICS CONFERENCE (BEC), 2020,
  • [38] Scalla: Structured Cluster Architecture for Low Latency Access
    Hanushevsky, Andrew
    Wang, Daniel L.
    2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW), 2012, : 1168 - 1175
  • [39] Design a low latency Arbiter for on chip Communication Architecture
    Khanam, Ruqaiya
    Sharma, Himanshu
    Gaur, Srishti
    2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA), 2015, : 1421 - 1426
  • [40] Improving communication latency with the write-only architecture
    Spacey, Simon
    Luk, Wayne
    Kelly, Paul H. J.
    Kuhn, Daniel
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2012, 72 (12) : 1617 - 1627