LATENCY COST AND ARCHITECTURE

被引：0
|
作者：
SENZIG, DN
TUNG, C
PANIGRAHI, VG
RAU, BR
WENSLEY, JH
HOLLANDER, GL
机构：
[1] HEWLETT PACKARD CO,SAN DIEGO,CA 92100
[2] IBM CORP,SAN DIEGO,CA
[3] BURROUGHS CORP,SAN DIEGO,CA
[4] STANFORD UNIV,STANFORD,CA
[5] STANFORD RES INST,STANFORD,CA
来源：
COMPUTER | 1976年 / 9卷 / 03期
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：8 / 10
页数：3
相关论文
共 50 条
  • [21] Duetto: Latency Guarantees at Minimal Performance Cost
    Mirosanlou, Reza
    Hassan, Mohamed
    Pellizzoni, Rodolfo
    PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, : 1136 - 1141
  • [22] CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
    Luo, Haocong
    Shahroodi, Taha
    Hassan, Hasan
    Patel, Minesh
    Yaǧlikçi, A. Giray
    Orosa, Lois
    Park, Jisung
    Mutlu, Onur
    Proceedings - International Symposium on Computer Architecture, 2020, 2020-May : 666 - 679
  • [23] CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
    Luo, Haocong
    Shahroodi, Taha
    Hassan, Hasan
    Patel, Minesh
    Yaglikci, A. Giray
    Orosa, Lois
    Park, Jisung
    Mutlu, Onur
    2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), 2020, : 666 - 679
  • [24] Low-Latency Networking: Architecture, Techniques, and Opportunities
    Zuo, Xutong
    Cui, Yong
    Wang, Mowei
    Xiao, Tianxiao
    Wang, Xin
    IEEE INTERNET COMPUTING, 2018, 22 (05) : 56 - 63
  • [25] LAWIN : a Latency-AWare InterNet Architecture for Latency Support on Best-Effort Networks
    Kobayashi, Katsushi
    2015 IEEE 16TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE SWITCHING AND ROUTING (HPSR), 2015, : 180 - 187
  • [26] A Flexible Polar Decoding Architecture With Adjustable Latency and Reliability
    Fujiwara, Shintaro
    Ochiai, Hideki
    IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY, 2024, 5 : 951 - 964
  • [27] A Compact and Low Latency SPM Architecture for ECC Cryptosystems
    Javeed, Khalid
    Sibai, Fadi N.
    El-Moursy, Ali
    IEEE ACCESS, 2024, 12 : 147552 - 147563
  • [28] Modeling Detection Latency with Collaborative Mobile Sensing Architecture
    Chin, Tai-Lin
    Ramanathan, Parameswaran
    Saluja, Kewal K.
    IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (05) : 692 - 705
  • [29] Chip multiprocessor architecture: Techniques to improve throughput and latency
    Olukotun, Kunle
    Hammond, Lance
    Laudon, James
    Synthesis Lectures on Computer Architecture, 2007, 3 : 1 - 149
  • [30] A Flexible Polar Decoding Architecture With Adjustable Latency and Reliability
    Fujiwara, Shintaro
    Ochiai, Hideki
    IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY, 2024, 5 : 951 - 964
12345