METASTABILITY OF CMOS LATCH FLIP-FLOP

This paper presents the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flop by using the ac small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) is measured, and the result verifies this new design approach experimentally. The power supply disturbance and temperature variation effects on the metastability are also measured and the data show that a 0.75 V change of power supply voltage (Vdd) and 75°C change of chip temperature cause four orders of magnitude difference in MTBF. The simulation results using the ac small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures. Therefore it confirms again that an ac small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. Finally the other parameters are discussed in terms of their effects on the latch/flip-flop’s susceptibility to the metastable state. © 1990 IEEE