共 7 条
- [1] An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages [J]. ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN, 2003, : 149 - 154
- [5] Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic [J]. SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2004, : 181 - 185
- [6] A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic [J]. 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2002, : 298 - 301
- [7] A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-logic [J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 781 - 784