A fault-tolerant and congestion-aware architecture for wireless networks-on-chip

被引:0
|
作者
Seyed Hassan Mortazavi
Reza Akbar
Farshad Safaei
Amin Rezaei
机构
[1] Shahid Beheshti University G.C.,Faculty of Computer Science and Engineering
[2] Northwestern University (NU),Department of Electrical Engineering and Computer Science
来源
Wireless Networks | 2019年 / 25卷
关键词
Network-on-chip; Hybrid wireless network-on-chip; Many-core system-on-chip; Reliability; Robustness; Congestion control management;
D O I
暂无
中图分类号
学科分类号
摘要
The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation complexities but also due to their relatively high utilization. In this paper, a new topology is presented to enhance the network reliability, and then a novel routing algorithm is proposed to tolerate both intermittent and permanent faults on wireless hubs. In the proposed approach, once a wireless hub becomes faulty, the best alternative adjustment hub will be indicated and all the packets that have high average hop-count are routed through this alternative hub. In comparison with the state-of-the-art works, the proposed approach shows significant improvements in terms of robustness, congestion management, and resilience.
引用
收藏
页码:3675 / 3687
页数:12
相关论文
共 50 条
  • [1] A fault-tolerant and congestion-aware architecture for wireless networks-on-chip
    Mortazavi, Seyed Hassan
    Akbar, Reza
    Safaei, Farshad
    Rezaei, Amin
    WIRELESS NETWORKS, 2019, 25 (06) : 3675 - 3687
  • [2] A Fault-Tolerant and Congestion-Aware Routing Algorithm for Networks-on-Chip
    Valinataj, Mojtaba
    Mohammadi, Siamak
    Plosila, Juha
    Liljeberg, Pasi
    PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 139 - 144
  • [3] A new Fault-tolerant and Congestion-aware Adaptive Routing Algorithm for Regular Networks-on-Chip
    Kia, Hamed S.
    Ababei, Cristinel
    2011 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2011, : 2465 - 2472
  • [4] A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip
    Liu, Yi
    Guo, Rujia
    Xu, Changqing
    Weng, Xiaodong
    Yang, Yintang
    IEEE EMBEDDED SYSTEMS LETTERS, 2022, 14 (04) : 203 - 206
  • [5] PARS - An Efficient Congestion-Aware Routing Method for Networks-on-Chip
    Chang, Xin
    Ebrahimi, Masoumeh
    Daneshtalab, Masoud
    Westerlund, Tomi
    Plosila, Juha
    2012 16TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2012, : 166 - 171
  • [6] Design of Fault-Tolerant and Reliable Networks-on-Chip
    Wang, Junshi
    Ebrahimi, Masoumeh
    Huang, Letian
    Jantsch, Axel
    Li, Guangjun
    2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, : 545 - 550
  • [7] Fault-Tolerant Routing Methodology for Networks-on-Chip
    Savva, S.
    2017 27TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2017,
  • [8] Fault-Tolerant Network Interfaces for Networks-on-Chip
    Fiorin, Leandro
    Sami, Mariagiovanna
    IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2014, 11 (01) : 16 - 29
  • [9] Dynamically Reconfigurable Architecture for Fault-tolerant 2D Networks-on-Chip
    Bahrebar, Poona
    Jalalvand, Azarakhsh
    Stroobandt, Dirk
    2017 26TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND NETWORKS (ICCCN 2017), 2017,
  • [10] Networks-on-chip: The quest for on-chip fault-tolerant communication
    Marculescu, R
    ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN, 2003, : 8 - 12