Fault-Tolerant Routing Methodology for Networks-on-Chip

Networks-on-Chip are vulnerable to a variety of manufacturing and design factors making them susceptible to disparate faults that cause corrupted message transfer or even catastrophic system failures, due to the central position of the NoC in the system. Therefore, a NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. The terminology of fault tolerant relates to a design capable to continue its operation, probably at a lower efficiency level, instead of failing utterly, when some part of the system fails. This abstract analyzes the main concept of my dissertation witch is the design of a systematic methodology for fault tolerant routing in 2D and 3D NoC, that promises to provide sufficient fault coverage with reasonable overhead in terms of hardware redundancy and performance (e.g. delay/power) degradation, given the designer's requirements and constraints.