Modeling and design of an ultra low-power NEMS relays: application to logic gate inverters

被引:0
|
作者
Hatem Samaali
Fehmi Najar
Amar Chaalane
机构
[1] University of Carthage,Applied Mechanics and Systems Research Laboratory (LR03ES06), Tunisia Polytechnic School
[2] University of Carthage,ISTIC
[3] FEMTO-ST,Micro Nano Sciences and Systems Department
[4] Badji Mokhtar University of Annaba,Physics Department
关键词
NEMS; Nanoinverter; Cantilever nanobeam; Ohmic contact; Transient pull-in; Low power;
D O I
暂无
中图分类号
学科分类号
摘要
In this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of the electrostatic force and the ohmic contact of the nanobeams’ tip with the fixed output electrode. The derived electromechanical model is used for electrical and energy analysis. Simulations are used to confirm the functionality of the inverter. The analysis of the switching energy showed very low power consumption compared to classical CMOS inverters. It is shown that the proposed inverter dissipates only 0.45 fJ to code a “1” logic-state and 0.023 fJ to code a “0” logic-state.
引用
收藏
页码:17 / 26
页数:9
相关论文
共 50 条
  • [41] Atom Switch Technology for Low-power Nonvolatile Logic Application
    Tada, M.
    Sakamoto, T.
    Miyamura, M.
    Banno, N.
    Okamoto, K.
    Hada, H.
    INTERNATIONAL SYMPOSIUM ON FUNCTIONAL DIVERSIFICATION OF SEMICONDUCTOR ELECTRONICS 2 (MORE-THAN-MOORE 2), 2014, 61 (06): : 57 - 64
  • [42] Low- and ultra low-power arithmetic units: Design and comparison
    Vratonjic, M
    Zeydel, BR
    Oklobdzija, VG
    2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2005, : 249 - 252
  • [43] Design of Low Power Multiplier Using Reversible Logic Gate
    Thakre, Ashish K.
    Chiwande, Sujata S.
    Chafale, Sumit D.
    2014 INTERNATIONAL CONFERENCE ON GREEN COMPUTING COMMUNICATION AND ELECTRICAL ENGINEERING (ICGCCEE), 2014,
  • [44] A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications
    Sengupta, Savio Jay
    Goswami, Bijoy
    Das, Pritam
    Sarkar, Subir Kumar
    Silicon, 2022, 14 (10): : 5091 - 5101
  • [45] A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications
    Savio Jay Sengupta
    Bijoy Goswami
    Pritam Das
    Subir Kumar Sarkar
    Silicon, 2022, 14 : 5091 - 5101
  • [46] A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications
    Sengupta, Savio Jay
    Goswami, Bijoy
    Das, Pritam
    Sarkar, Subir Kumar
    SILICON, 2022, 14 (10) : 5091 - 5101
  • [47] Novel low-voltage low-power full-swing BiNMOS logic gate
    Margala, M
    Durdle, NG
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1998, 84 (05) : 487 - 498
  • [48] LOW-POWER BIPOLAR TECHNIQUE BEGETS LOW-POWER LSI LOGIC
    XYLANDER, MP
    ELECTRONICS, 1972, 45 (16): : 80 - &
  • [49] Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
    Shahrjerdi, D
    Hekmatshoar, B
    Khakifirooz, A
    Afzali-Kusha, A
    INTEGRATION-THE VLSI JOURNAL, 2005, 38 (03) : 505 - 513
  • [50] Ultra low-power radio design for wireless sensor networks
    Enz, Christian C.
    Scolari, Nicola
    Yodprasit, Uroschanit
    2005 IEEE INTERNATIONAL WORKSHOP ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY, PROCEEDINGS: INTEGRATED CIRCUITS FOR WIDEBAND COMMUNICATION AND WIRELESS SENSOR NETWORKS, 2005, : 1 - 17