Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

被引：8

作者：

Saha P. ^{[1
]}

Banerjee P. ^{[1
]}

Dash D.K. ^{[1
]}

Sarkar S.K. ^{[1
]}

机构：

[1] Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata

来源：

Journal of Materials Engineering and Performance | 2018年 / 27卷 / 06期

关键词：

asymmetric; DIBL; junctionless; Silicon-on-Nothing; subthreshold swing; threshold voltage roll-off;

D O I：

10.1007/s11665-018-3281-2

中图分类号：

学科分类号：

摘要：

This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson’s equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model. © 2018, ASM International.

引用

页码：2708 / 2712

页数：4

共 50 条

[31] Physics based capacitance modeling of short-channel double-gate MOSFETs
Borli, H.
Vinkenes, K.
Fjeldly, T. A.
PHYSICA STATUS SOLIDI C - CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 5, NO 12 2008, 2008, 5 (12): : 3643 - 3646
[32] Symmetrical unified compact model of short-channel double-gate MOSFETs
Papathanasiou, K.
Theodorou, C. G.
Tsormpatzoglou, A.
Tassis, D. H.
Dimitriadis, C. A.
Bucher, M.
Ghibaudo, G.
SOLID-STATE ELECTRONICS, 2012, 69 : 55 - 61
[33] Compact subthreshold slope modelling of short-channel double-gate MOSFETs
Monga, U.
Fjeldly, T. A.
ELECTRONICS LETTERS, 2009, 45 (09) : 476 - 477
[34] Short-Channel Double-Gate FETs with Atomically Precise Graphene Nanoribbons
Mutlu, Z.
Lin, Y.
Barin, G. B.
Zhang, Z.
Pitner, G.
Wang, S.
Darawish, R.
Di Giovannantonio, M.
Wang, H.
Cai, J.
Passlack, M.
Diaz, C. H.
Narita, A.
Muellen, K.
Fischer, F. R.
Bandaru, P.
Kummel, A. C.
Ruffieux, P.
Fasel, R.
Bokor, J.
2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
[35] A general physical model for short-channel double-gate SOI MOSFETS
Li, ZM
Woo, JCS
1997 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 86 - 87
[36] DICE: A beneficial short-channel effect in nanoscale double-gate MOSFETs
Chouksey, Siddharth
Fossum, Jerry G.
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (03) : 796 - 802
[37] Compact Model for Short-Channel Junctionless Accumulation Mode Double Gate MOSFETs
Holtij, Thomas
Graef, Michael
Marie Hain, Franziska
Kloes, Alexander
Iniguez, Benjamin
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) : 288 - 299
[38] Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance
Wagaj, S. C.
Chavan, Y. V.
SMART TRENDS IN INFORMATION TECHNOLOGY AND COMPUTER COMMUNICATIONS, SMARTCOM 2016, 2016, 628 : 27 - 38
[39] A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure
Jin, Xiaoshi
Liu, Xi
Kwon, Hyuck-In
Lee, Jung-Hee
Lee, Jong-Ho
SOLID-STATE ELECTRONICS, 2013, 82 : 77 - 81
[40] Short channel and back-gate coupling effects in silicon-on-nothing (SON) MOSFETs
Pretet, J
Cristoloveanu, S
Skotnicki, T
Monfray, S
2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 122 - 123

← 1 2 3 4 5 →