Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

被引：0
|
作者：
Thamizharasan, V. [1 ]
Parthipan, V. [2 ]
机构：
[1] Erode Sengunthar Engn Coll, Dept ECE, Erode, India
[2] Sri Eshwar Coll Engn, Dept ECE, Coimbatore, India
来源：
SCIENTIFIC REPORTS | 2024年 / 14卷 / 01期
关键词：
Hybrid; Multiplier; Compressor; Xilinx; Field programmable gate array (FPGA); Spartan6;
D O I：
10.1038/s41598-024-58482-0
中图分类号：
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号：
07 ; 0710 ; 09 ;
摘要：
In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA-spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).
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页数：11
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