ASIC design of IPSec hardware accelerator for network security

被引：6

作者：

Ha, CS ^{[1
]}

Lee, JH ^{[1
]}

Leem, DS ^{[1
]}

Park, MS ^{[1
]}

Choi, BY ^{[1
]}

机构：

[1] Dong Eui Univ, Dept Comp Engn, Pusan 614714, South Korea

来源：

PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS | 2004年

关键词：

D O I：

10.1109/APASIC.2004.1349439

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes ASIC design of IPSec hardware accelerator for network security which can execute tunnel-mode AH and ESP algorithm of IPSec protocol suite. The processor supports AES-128/192/256, TDES, HMAC-MD5 and HMAC-SHA-1 algorithm to encrypt and authenticate the packet data and operates as hardware coprocessor to accelerate cryptographic routine of FreeS/WAN software. The IPSec hardware accelerator consists of AMBA interface, 2KB packet memory, parameter registers, global controller, and cryptographic module. It was designed using 0.25um CMOS standard cell library and consists of about 78K gates and 2KB memory. Its throughput of ESP-AES128-HMAC-SHA1 operation is approximately 200 Mbps at 125Mhz for 120-byte test packet.

引用

页码：168 / 171

页数：4

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