Efficient gate delay modeling for large interconnect loads

被引：13
|
作者：
Kahng, AB [1 ]
Muddu, S [1 ]
机构：
[1] UNIV CALIF LOS ANGELES,DEPT COMP SCI,LOS ANGELES,CA 90095
来源：
1996 IEEE MULTI-CHIP MODULE CONFERENCE, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/MCMC.1996.510795
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：202 / 207
页数：6
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