Modeling the effective capacitance of interconnect loads for predicting CMOS gate slew

In deep submicron designs, predicting gate stews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect loads. Many C-eff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C-eff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C-eff of interconnect load for gate slew. We firstly establish a new expression for C-eff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C-eff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C-eff in 0.8Vdd point, C-eff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.