3D assembly technology for hybrid integration of heterogenous devices

For heterogeneous chip technologies (Power/Signal, Electronics/MEMS, CMOS/III-V's,...) the three dimensional integration of hybrid assembled chips is a viable approach to overcome the issues encountered here. Especially when the interconnects become very dense (high I/O's) or signal voltages from chip to chip are vastly different, a non-ohmic contact via capacitive coupling can be a solution to overcome this issue. Submicron accuracies in the z-direction and low-micron accuracies in x/y are required to fulfill the needs of such a capacitive contact for 8x8 mu m(2) sized pad arrays. The authors have successfully developed a chip, the interconnect scheme and the assembly process that allows the capacitive coupling of high I/O chips for electronic, MEMS and heterogeneous hybrid devices. The 3D Chip Stack was afterwards assembled on a test PCB with through via wirebonding. Envisioned concept shows the use of backside contacts e.g. PWR/GND/CLK for the top chip to be realized by integrated through via chip manufacturing as used in MEMS/MOEMS technology.