Off current adjustment in ultra-thin SOI MOSFETs

被引：3

作者：

Hartwich, J ^{[1
]}

Dreeskornfeld, L ^{[1
]}

Hofmann, F ^{[1
]}

Kretz, J ^{[1
]}

Landgraf, E ^{[1
]}

Luyken, RJ ^{[1
]}

Specht, M ^{[1
]}

Städele, M ^{[1
]}

Schulz, T ^{[1
]}

Rösner, W ^{[1
]}

Risch, L ^{[1
]}

机构：

[1] Infineon Technol AG, Corp Res, D-81730 Munich, Germany

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSDER.2004.1356550

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25nm and silicon thicknesses of 25nm and 16nm have been analysed. Gate oxide thicknesses of 2.5nm and 1.8nm have also been.f'current adjustment by compared. We demonstrate of channel implantation whereby, together with work,function engineering, a suitable solution for multiple Vt SOI CMOS technology could be provided.

引用

页码：305 / 308

页数：4

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