Testability preserving and enhancing transformations for robust delay fault testability

被引：0

作者：

Karkare, A ^{[1
]}

Singla, M ^{[1
]}

Jain, A ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Comp Sci & Engn, Kanpur, Uttar Pradesh, India

来源：

ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).

引用

页码：370 / 373

页数：4

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