Testability preserving and enhancing transformations for robust delay fault testability

被引：0

作者：

Karkare, A ^{[1
]}

Singla, M ^{[1
]}

Jain, A ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Comp Sci & Engn, Kanpur, Uttar Pradesh, India

来源：

ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).

引用

页码：370 / 373

页数：4

共 50 条

[21] Testability Transformations For Existing APIs
Arcuri, Andrea
Galeotti, Juan P.
[J]. 2020 IEEE 13TH INTERNATIONAL CONFERENCE ON SOFTWARE TESTING, VALIDATION AND VERIFICATION (ICST 2020), 2020, : 153 - 163
[22] Specification transformations and design for testability
Karoui, K
Dssouli, R
Cherkaoui, O
[J]. IEEE GLOBECOM 1996 - CONFERENCE RECORD, VOLS 1-3: COMMUNICATIONS: THE KEY TO GLOBAL PROSPERITY, 1996, : 680 - 685
[23] Enhancing Search-based Testing with Testability Transformations for Existing APIs
Arcuri, Andrea
Galeotti, Juan P.
[J]. ACM TRANSACTIONS ON SOFTWARE ENGINEERING AND METHODOLOGY, 2022, 31 (01)
[24] On cancelling the effects of logic sharing for improved path delay fault testability
Pomeranz, I
Reddy, SM
[J]. INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 357 - 366
[25] Design for Delay Fault Testability of 2-Rail Logic Circuits
Katoh, Kentaroh
Namba, Kazuteru
Ito, Hideo
[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2009, E92D (02): : 336 - 341
[26] Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Angela Krstić
Kwang-Ting Cheng
[J]. Journal of Electronic Testing, 1997, 11 : 43 - 54
[27] Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Namba, Kazuteru
Ito, Hideo
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (09) : 2295 - 2303
[28] RANDOM PATTERN TESTABILITY OF DELAY FAULTS
SAVIR, J
MCANNEY, WH
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (03) : 291 - 300
[29] Evaluation of delay fault testability of LUT functions for improved efficiency of FPGA testing
Krasniewski, A
[J]. EUROMICRO SYMPOSIUM ON DIGITAL SYSTEMS DESIGN, PROCEEDINGS, 2001, : 310 - 317
[30] Resynthesis of combinational circuits for path count reduction and for path delay fault testability
Krstic, A
Cheng, KT
[J]. EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS, 1996, : 486 - 490

← 1 2 3 4 5 →