Testability preserving and enhancing transformations for robust delay fault testability

被引：0

作者：

Karkare, A ^{[1
]}

Singla, M ^{[1
]}

Jain, A ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Comp Sci & Engn, Kanpur, Uttar Pradesh, India

来源：

ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).

引用

页码：370 / 373

页数：4

共 50 条

[1] ON LOCAL TRANSFORMATIONS AND PATH DELAY-FAULT TESTABILITY
HENGSTER, H
DRECHSLER, R
BECKER, B
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1995, 7 (03): : 173 - 191
[2] Enhancing delay fault testability for iterative logic arrays
Lu, SK
Yeh, CH
[J]. 2002 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2002, : 283 - 290
[3] DELAY-FAULT TESTABILITY PRESERVATION OF THE CONCURRENT DECOMPOSITION AND FACTORIZATION TRANSFORMATIONS
ELMALEH, AH
RAJSKI, J
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (05) : 582 - 590
[4] Design for primitive delay fault testability
Krstic, A
Chakradhar, ST
Chen, KT
[J]. ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 436 - 445
[5] Path delay fault testability analysis
Sosnowski, J
Wabia, T
Bech, T
[J]. IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 338 - 346
[6] Enhancing delay fault testability for FIR filters based on realistic sequential cell fault model
Lu, SK
Lu, MJ
[J]. DELTA 2004: SECOND IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST APPLICATIONS, PROCEEDINGS, 2004, : 416 - 418
[7] Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
Nowick, SM
Jha, NK
Cheng, FC
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (12) : 1514 - 1521
[8] Delay fault testability modeling with temporal logic
Westerman, G
Heath, JR
Stroud, CE
[J]. AUTOTESTCON '97 - IEEE SYSTEMS READINESS TECHNOLOGY CONFERENCE, 1997 IEEE AUTOTESTCON PROCEEDINGS, 1997, : 376 - 382
[9] BDD circuit optimization for path delay fault testability
Fey, G
Shi, J
Drechsler, R
[J]. PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN, 2004, : 168 - 172
[10] Synthesis for parallel scan: Applications to partial scan and robust path delay fault testability
Bhatia, S
Jha, NK
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (02) : 228 - 243

← 1 2 3 4 5 →