An accelerator for double precision floating point operations

被引：2

作者：

Danese, G ^{[1
]}

De Lotto, I ^{[1
]}

Leporati, F ^{[1
]}

Scaricabarozzi, M ^{[1
]}

Spelgatti, A ^{[1
]}

机构：

[1] Univ Pavia, Dipartimento Informat & Sistemist, INFM, I-27100 Pavia, Italy

来源：

ELEVENTH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/EMPDP.2003.1183566

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe DPFPA (Double Precision Floating Point Accelerator) an FPGA based coprocessor interfaced to the CPU through the PCI bus; it is conceived to accelerate the evaluation of double precision floating point operations. This coprocessor is based on two double precision floating point units: a pipelined adder and a pipelined multiplier. The work is part of a global project aimed to design and build a parallel system made up by a cluster of accelerated workstations. First estimations of performance have been obtained, using a similar board developed at Fermilab (Batavia, IL) with less recent components and working at half the frequency with respect to DPFPA. Even in this case, a substantial acceleration with respect to the execution on Intel's CPU based mother-board was observed.

引用

页码：57 / 63

页数：7

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