Low power multiplier designs based on improved column bypassing schemes

In this paper, we proposed two novel low power multiplier designs based on improved column bypassing schemes. The power saving comes from bypassing signals along those adder columns in the array multiplier corresponding to zero bits in the multiplicand. Spurious signal switching activities can then be eliminated when bypassing occurs. The proposed designs successfully resolve the adverse DC power consumption problem in previous research due to troublesome tri-state input buffers. Our designs also implement the bypassing logic cleverly via (CMOS)-M-2 circuitry and eliminate the costly (both circuit- and power-wise) multiplexers. The circuit overheads of the proposed designs can be as low as 10% compared with 54% in [7]. Simulations results also indicate previous work may fail to gain any power saving (and actually deteriorate power consumption) when Vdd is higher than 1.6V. Our designs, nonetheless, achieve power saving consistently in different working conditions and the best saving can be as much as 29%.