A modular pipelined Macro-Block for high-speed digital filtering applications

被引：0

作者：

Gürkaynak, FK ^{[1
]}

Leblebici, Y ^{[1
]}

机构：

[1] Worcester Polytech Inst, Dept Elect & Comp Engn, Worcester, MA 01609 USA

来源：

42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A programmable, fully pipelined macro-block (Aries), that can be used as a modular convolution engine to design digital FIR filters of any size with a minimum clock cycle of 20 ns, is presented. The proposed module is very compact and occupies an active silicon area of less than 1.5 mm(2) in a conventional 0.8 mu m digital CMOS technology, allowing a large number of Aries macro-blocks to be easily embedded in a larger design to realize digital filters of any dimensions.

引用

页码：740 / 743

页数：4

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