Path delay testing: Variable-clock versus rated-clock

被引:0
|
作者
Majumder, S [1 ]
Agrawal, VD [1 ]
Bushnell, ML [1 ]
机构
[1] Rutgers State Univ, Dept ECE, Piscataway, NJ 08855 USA
来源
ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-elect method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.
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页码:470 / 475
页数:6
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