共 50 条
- [42] Branch prediction, instruction-window size, and cache size: Performance trade-offs and simulation techniques IEEE Trans Comput, 11 (1260-1281):
- [43] Phase-based Dynamic Instruction Window Optimization for Embedded Systems 2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2016, : 397 - 402
- [44] A Hardware-assisted Translation Cache for Dynamic Binary Translation in Embedded Systems 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA), 2018, : 307 - 312
- [45] Using Dynamic, Full Cache Locking and Genetic Algorithms for Cache Size Minimization in Multitasking, Preemptive, Real-Time Systems THEORY AND PRACTICE OF NATURAL COMPUTING, 2013, 8273 : 157 - 168
- [46] Dynamic round-robin task scheduling to reduce cache misses for embedded systems 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1332 - +
- [49] Drowsy instruction caches Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction 35TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-35), PROCEEDINGS, 2002, : 219 - 230
- [50] Timing Prediction for Dynamic Application Migration on Multi-Core Embedded Systems 2018 IEEE 4TH INTERNATIONAL CONFERENCE ON BIG DATA SECURITY ON CLOUD (BIGDATASECURITY), 4THIEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE AND SMART COMPUTING, (HPSC) AND 3RD IEEE INTERNATIONAL CONFERENCE ON INTELLIGENT DATA AND SECURITY (IDS), 2018, : 159 - 164