Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems

被引:6
|
作者
Qiu, Keni [1 ]
Zhao, Mengying [1 ]
Xue, Chun Jason [1 ]
Orailoglu, Alex [2 ]
机构
[1] City Univ Hong Kong, Dept Comp Sci, Hong Kong, Hong Kong, Peoples R China
[2] Univ Calif San Diego, Dept Comp Sci & Engn, San Diego, CA 92103 USA
关键词
Design; Algorithms; Performance; Dynamic cache locking; branch prediction; instruction cache; execution region partitioning; system performance;
D O I
10.1145/2660492
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Cache locking is a cache management technique to preclude the replacement of locked cache contents. Cache locking is often adopted to improve cache access predictability in Worst-Case Execution Time (WCET) analysis. Static cache locking methods have been proposed recently to improve Average-Case Execution Time (ACET) performance. This article presents an approach, Branch Prediction-directed Dynamic Cache Locking (BPDCL), to improve system performance through cache conflict miss reduction. In the proposed approach, the control flow graph of a program is first partitioned into disjoint execution regions, then memory blocks worth locking are determined by calculating the locking profit for each region. These two steps are conducted during compilation time. At runtime, directed by branch predictions, locking routines are prefetched into a small high-speed buffer. The predetermined cache locking contents are loaded and locked at specific execution points during program execution. Experimental results show that the proposed BPDCL method exhibits an average improvement of 25.9%, 13.8%, and 8.0% on cache miss rate reduction in comparison to cases with no cache locking, the static locking method, and the dynamic locking method, respectively.
引用
收藏
页数:24
相关论文
共 50 条
  • [31] Integrating Task Scheduling and Cache Locking for Multicore Real-Time Embedded Systems
    Zheng, Wenguang
    Wu, Hui
    Nie, Chuanyao
    ACM SIGPLAN NOTICES, 2017, 52 (05) : 71 - 80
  • [32] Evaluation of I-Cache locking technique for real-time embedded systems
    Asaduzzaman, Abu
    Limbachiya, Niranjan
    Mahgoub, Imad
    Sibai, Fadi N.
    2007 INNOVATIONS IN INFORMATION TECHNOLOGIES, VOLS 1 AND 2, 2007, : 214 - +
  • [33] Compression-aware dynamic cache reconfiguration for embedded systems
    Hajimiri, Hadi
    Rahmani, Kamran
    Mishra, Prabhat
    SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 2012, 2 (02): : 71 - 80
  • [34] Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems
    Ni, Fan
    Long, Xiang
    Wan, Han
    Gao, Xiaopeng
    PLOS ONE, 2013, 8 (12):
  • [35] Dual-access way-prediction cache for embedded systems
    Chu, Yul
    Park, Jin Hwan
    EURASIP JOURNAL ON EMBEDDED SYSTEMS, 2014, 2014 (01)
  • [36] TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems
    Adegbija, Tosiron
    Gordon-Ross, Ann
    COMPUTERS, 2018, 7 (01)
  • [37] DYNAMIC TIME TUNING FOR WAY PREDICTION CACHE IN LOW POWER EMBEDDED PROCESSORS
    Zhang, Chi
    Wang, Xiang
    Bu, Chunguang
    Wang, Lin
    Ji, Huihui
    Xia, Tongsheng
    2009 IEEE/AIAA 28TH DIGITAL AVIONICS SYSTEMS CONFERENCE, VOLS 1-3, 2009, : 1749 - 1756
  • [38] Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
    Asaduzzaman, Abu
    Sibai, Fadi N.
    Rani, Manira
    JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 56 (4-6) : 151 - 162
  • [39] Application specific low latency instruction cache for NAND flash memory based embedded systems
    Lee, Kwangyoon
    Orailoglu, Alex
    2008 SYMPOSIUM ON APPLICATION SPECIFIC PROCESSORS, 2008, : 69 - 74
  • [40] Optimizing CAM-based instruction cache designs for low-power embedded systems
    Aragon, Juan L.
    Veidenbaum, Alexander V.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2008, 54 (12) : 1155 - 1163