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- [1] A single-electron-transistor logic gate family and its application - Part I: Basic components for binary, multiple-valued and mixed-mode logic 34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 262 - 268
- [2] A single-electron-transistor logic gate family and its application - Part II: Design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions 34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 269 - 274
- [3] Family of fast mixed arithmetic logic transforms for multiple-valued input binary functions 1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 1996, : 24 - 29
- [4] Experimental and simulation studies of single-electron-transistor-based multiple-valued logic 33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2003, : 259 - 266
- [5] A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 579 - 582
- [6] Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 385 - 388
- [7] A merged single-electron transistor and metal-oxide-semiconductor transistor logic for interface and multiple-valued functions JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2002, 41 (4B): : 2566 - 2568
- [8] An error correction method for binary and multiple-valued logic 2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL), 2011, : 105 - 110
- [10] Synthesis of double pass-transistor logic network applied to multiple-valued logic Zhejiang Daxue Xuebao (Gongxue Ban), 2007, 8 (1307-1311+1328):