A single-electron-transistor logic gate family for binary, multiple-valued and mixed-mode logic

被引:0
|
作者
Degawa, K [1 ]
Aoki, T
Higuchi, T
Inokawa, H
Takahashi, Y
机构
[1] Tohoku Univ, Dept Math & Comp Sci, Grad Sch Infromat Sci, Sendai, Miyagi 9808579, Japan
[2] Tohoku Inst Technol, Dept Elect, Fac Engn, Sendai, Miyagi 9828577, Japan
[3] NTT Corp, NTT Basic Res Labs, Atsugi, Kanagawa 2430198, Japan
[4] Hokkaido Univ, Grad Sch Informat Sci & Technol, Sapporo, Hokkaido 0600814, Japan
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2004年 / E87C卷 / 11期
关键词
single-electron transistors; multiple-valued logic; quantum devices; logic circuits; parallel counters;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a model-based study of SET (SingleElectron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Nlalued) and mixed-mode logic circuits. The use of SETS combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETS. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-NIV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.
引用
收藏
页码:1827 / 1836
页数:10
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