A simplified architecture for modulo (2n+1) multiplication

被引：0
|
作者：
Ma, YT [1 ]
机构：
[1] Chinese Acad Sci, Comp Technol Inst, Ctr High Performance Comp, Beijing 100080, Peoples R China
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1998年 / 47卷 / 03期
关键词：
convolution; Fermat number transform; RNS arithmetic; modulo (2(n)+1) multiplication; Booth's algorithm; Wallace tree; carry save adder; CSA array; carry lookahead adder;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The module (2(n) + 1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2(n) + 1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the module (2(n) + 1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n greater than or equal to 16).
引用
收藏
页码：333 / 337
页数：5
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