Design of GF(2m) multiplier using its subfields

被引：2
|
作者：
Cho, YS [1 ]
Park, SK [1 ]
机构：
[1] Hanyang Univ, Dept Elect Commun Engn, Seoul 133791, South Korea
来源：
ELECTRONICS LETTERS | 1998年 / 34卷 / 07期
关键词：
D O I：
10.1049/el:19980521
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A design method of a GF(2(m)) multiplier using its subfields is presented. This method can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. It has an advantageous feature, namely that a trade-off between hardware complexity and delay time can be achieved.
引用
收藏
页码：650 / 651
页数：2
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