A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

被引：160

作者：

Kawaguchi, H ^{[1
]}

Sakurai, T ^{[1
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 05期

关键词：

differential circuit; flip-flops; leak current; low-power CMOS circuit; low-voltage CMOS circuit; RC bus; RC delay; RC interconnect;

D O I：

10.1109/4.668997

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A reduced clock-swing hip-hop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special hip-hop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.

引用

页码：807 / 811

页数：5

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