An Overview of Selected Heterogeneous and Reconfigurable Architectures

被引:3
|
作者
Stojanovic, Sasa [1 ]
Bojic, Dragan [1 ]
Bojovic, Miroslav [1 ]
机构
[1] Univ Belgrade, Sch Elect Engn, Belgrade, Serbia
关键词
ACCELERATION; PLATFORM; GPU;
D O I
10.1016/bs.adcom.2014.11.003
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Node level heterogeneous architectures are gaining popularity because of their excellent performance exhibited in real world applications from various domains. The main advantages of these architectures are better price-performance and power-performance ratios compared to traditional symmetric CPU architectures. This article presents an overview of most interesting node level heterogeneous architectures, focusing on some common architectures, such as the NVIDIA and the ATI graphics processing units, the Cell Broadband Engine Architecture, the ClearSpeed processor, the field programmable gate array accelerator solutions from Maxeler MaxNodes, the SGI systems (RASC), and the Convey Hybrid-Core Computer. The presentation encompasses hardware resources and available software development tools for each of the mentioned architectures with both qualitative and quantitative comparisons. Toward the conclusion, the authors express their viewpoint on the future of heterogeneous computing.
引用
收藏
页码:1 / 45
页数:45
相关论文
共 50 条
  • [21] Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
    Warrier, Rakesh
    Zhang, Wei
    Vun, Chan Hua
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2017, 36 (09) : 3799 - 3824
  • [22] Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
    Rakesh Warrier
    Wei Zhang
    Chan Hua Vun
    Circuits, Systems, and Signal Processing, 2017, 36 : 3799 - 3824
  • [23] Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
    Dasu, Aravind
    Cardoso, Joao M. P.
    Bozorgzadeh, Eli
    Becker, Juergen
    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2011, 2011
  • [24] Reconfigurable Architectures for GNSS Receiver
    Khatri, Kriti
    Gajjar, Nagendra
    3RD NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE 2012), 2012,
  • [25] A modeling method for reconfigurable architectures
    Bossuet, L
    Gogniat, G
    Diguet, JP
    Philippe, JL
    SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, 2003, : 170 - 179
  • [26] Coarse grain reconfigurable architectures
    Hartenstein, R
    PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 564 - 569
  • [27] Reconfigurable Architectures and Emerging Technologies
    Clermidy, Fabien
    2013 IEEE FAIBLE TENSION FAIBLE CONSOMMATION (FTFC), 2013,
  • [28] Reconfigurable architectures for network processing
    Sezer, S
    McLoone, M
    McCanny, J
    2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 75 - 83
  • [29] Reconfigurable architectures workshop (RAW)
    2017, Institute of Electrical and Electronics Engineers Inc.
  • [30] Reconfigurable Architectures Workshop (RAW)
    Becker, Jurgen
    Vaidyanathan, Ramachandran
    Santambrogio, Marco
    Torresen, Jim
    Sass, Ron
    Leong, Philip
    Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, 2014, : 109 - 110