An Overview of Selected Heterogeneous and Reconfigurable Architectures

被引:3
|
作者
Stojanovic, Sasa [1 ]
Bojic, Dragan [1 ]
Bojovic, Miroslav [1 ]
机构
[1] Univ Belgrade, Sch Elect Engn, Belgrade, Serbia
关键词
ACCELERATION; PLATFORM; GPU;
D O I
10.1016/bs.adcom.2014.11.003
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Node level heterogeneous architectures are gaining popularity because of their excellent performance exhibited in real world applications from various domains. The main advantages of these architectures are better price-performance and power-performance ratios compared to traditional symmetric CPU architectures. This article presents an overview of most interesting node level heterogeneous architectures, focusing on some common architectures, such as the NVIDIA and the ATI graphics processing units, the Cell Broadband Engine Architecture, the ClearSpeed processor, the field programmable gate array accelerator solutions from Maxeler MaxNodes, the SGI systems (RASC), and the Convey Hybrid-Core Computer. The presentation encompasses hardware resources and available software development tools for each of the mentioned architectures with both qualitative and quantitative comparisons. Toward the conclusion, the authors express their viewpoint on the future of heterogeneous computing.
引用
收藏
页码:1 / 45
页数:45
相关论文
共 50 条
  • [1] An overview of Selected Hybrid and Reconfigurable Architectures
    Stojanovic, Sasa
    Bojic, Dragan
    Bojovic, Miroslav
    Valero, Mateo
    Milutinovic, Veljko
    2012 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2012, : 444 - 449
  • [2] Task placement for heterogeneous reconfigurable architectures
    Koester, M
    Porrmann, M
    Kalte, H
    FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings, 2005, : 43 - 50
  • [3] Heterogeneous reconfigurable architectures for machine learning dataflows
    Oliveira, Westerley C.
    Canesche, Michael
    Reis, Lucas
    Nacif, Jose Augusto M.
    Ferreira, Ricardo S.
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2023, 35 (17):
  • [4] Analysis of reconfigurable and heterogeneous architectures in the communication domain
    Feldkämper, HT
    Gemmeke, T
    Blume, H
    Noll, TG
    1ST IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS FOR COMMNICATIONS, PROCEEDINGS, 2002, : 190 - 193
  • [5] Online task placement algorithm for heterogeneous reconfigurable architectures
    Li, Dehua
    Wang, Binqiang
    Huang, Wanwei
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2010, 22 (10): : 1679 - 1686
  • [6] Towards a Guided Design Flow for Heterogeneous Reconfigurable Architectures
    Bostelmann, Timm
    Sawitzki, Sergei
    2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2015,
  • [7] A Reconfigurable Simulator for Large-scale Heterogeneous Multicore Architectures
    Meng, Jiayuan
    Skadron, Kevin
    IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS 2011), 2011, : 119 - 120
  • [8] Coarse Grained Reconfigurable Architectures in the Past 25 Years: Overview and Classification
    Wijtvliet, Mark
    Waeijen, Luc
    Corporaal, Henk
    PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (SAMOS), 2016, : 235 - 244
  • [9] Precision- and Accuracy-Reconfigurable Processor Architectures-An Overview
    Brand, Marcel
    Hannig, Frank
    Keszocze, Oliver
    Teich, Juergen
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (06) : 2661 - 2666
  • [10] Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures
    Sousa, Ericles
    Gangadharan, Deepak
    Hannig, Frank
    Teich, Juergen
    2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, : 74 - 81