High temperature single-hole silicon transistors

被引:0
|
作者
Bagraev, NT [1 ]
Gehlhoff, W [1 ]
Klyachkin, LE [1 ]
Malyarenko, AM [1 ]
Naser, A [1 ]
Romanov, VV [1 ]
机构
[1] AF Ioffe Phys Tech Inst, St Petersburg 194021, Russia
关键词
D O I
10.1117/12.299589
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
We present the first findings of the quantized conductance, EPR-EDEPR and NMR techniques which reveal the spin-dependent confinement and quantization phenomena in the silicon quantum wires created by the electrostatic ordering of the self-assembly dipole boron (B+ - B-) centres. These C-3v symmetry dipole impurity centres are regularly arranged along the edges of self-assembly longitudinal and lateral quantum wells (LQW and LaQW) which are naturally formed in the p(+)-diffusion profile inside ultra-shallow silicon n(+)-p(+)-p and n(+)-p(+)-n structures. A negative magnetoresistance that is evidence of the spin-dependent weak localization in self-assembly quantum wells at low electric fields is studied. The presence of natural quantum-size contacts inside self-assembly quantum wells is exhibited using the quantized conductance technique in weak magnetic fields.
引用
收藏
页码:166 / 174
页数:9
相关论文
共 50 条
  • [1] High-temperature single-hole silicon transistors
    Bagraev, NT
    Klyachkin, LE
    Malyarenko, AM
    Gehlhoff, W
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 1998, 23 (06) : 1333 - 1338
  • [2] Room temperature single-hole silicon memory
    Bagraev, NT
    Bouravleuv, AD
    Klyachkin, LE
    Malyarenko, AM
    Rykov, SA
    [J]. PHYSICS OF LOW-DIMENSIONAL STRUCTURES, 2000, 9-10 : 51 - 59
  • [3] Room temperature single-hole silicon memory cell
    Bagraev, NT
    Bouravleuv, AD
    Klyachkin, LE
    Malyarenko, AM
    Rykov, SA
    [J]. FOURTH INTERNATIONAL WORKSHOP ON NONDESTRUCTIVE TESTING AND COMPUTER SIMULATIONS IN SCIENCE AND ENGINEERING, 2001, 4348 : 125 - 128
  • [4] Tunneling barrier structures in room-temperature operating silicon single-electron and single-hole transistors
    Saitoh, Masumi
    Majima, Hideaki
    Hiramoto, Toshiro
    [J]. Saitoh, M. (masumi@nano.iis.u-tokyo.ac.jp), 1600, Japan Society of Applied Physics (42): : 2426 - 2428
  • [5] Tunneling barrier structures in room-temperature operating silicon single-electron and single-hole transistors
    Saitoh, M
    Majima, H
    Hiramoto, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2003, 42 (4B): : 2426 - 2428
  • [6] Room-temperature operation of current switching circuit using integrated silicon single-hole transistors
    Saitoh, M
    Harata, H
    Hiramoto, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2005, 44 (8-11): : L338 - L341
  • [7] Control of full width at half maximum of Coulomb oscillation in silicon single-hole transistors at room temperature
    Miyaji, Kousuke
    Hiramoto, Toshiro
    [J]. APPLIED PHYSICS LETTERS, 2007, 91 (05)
  • [8] Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors
    Miyaji, K
    Saitoh, M
    Hiramoto, T
    [J]. APPLIED PHYSICS LETTERS, 2006, 88 (14)
  • [9] Room-temperature transient carrier transport in germanium single-hole/electron transistors
    Liao, WM
    Li, PW
    Kuo, DMT
    Lai, WT
    [J]. APPLIED PHYSICS LETTERS, 2006, 88 (18)
  • [10] Silicon single-hole transistor with large Coulomb blockade oscillations and high voltage gain at room temperature
    Harata, H
    Saitoh, M
    Hiramoto, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2005, 44 (20-23): : L640 - L642