共 50 条
- [1] Design of Deep Sub-Micron CMOS Circuits and Design Methodologies for High Performance Microprocessor [J]. 2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : XLVI - XLVIII
- [2] IDDT test methodologies for very deep sub-micron CMOS circuits [J]. FIRST IEEE INTERNATION WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2002, : 403 - 407
- [3] Robust design of deep sub-micron CMOS wireless SoC [J]. 2008 IEEE RADIO AND WIRELESS SYMPOSIUM, VOLS 1 AND 2, 2008, : 61 - 64
- [4] An algorithmic approach for Leakage Current Reduction in Deep Sub-micron CMOS Circuits [J]. 2014 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, COMPUTERS AND COMMUNICATIONS (ICAECC), 2014,
- [5] Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [J]. Falconi, C. (falconi@eln.uniroma2.it), Circuits and Systems Society, IEEE CASS; Science Council of Japan; The Inst. of Electronics, Inf. and Communication Engineers, IEICE; The Institute of Electrical and Electronics Engineers, Inc., IEEE (Institute of Electrical and Electronics Engineers Inc.):
- [6] Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 228 - 231
- [7] Analysis of iDDT for defect detection and classification in very deep sub-micron CMOS circuits [J]. 6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XVII, PROCEEDINGS: INDUSTRIAL SYSTEMS AND ENGINEERING III, 2002, : 539 - 544
- [8] Analysis of ground bounce in deep sub-micron circuits [J]. 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 110 - 116
- [10] Analytic modeling of interconnects for deep sub-micron circuits [J]. ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 835 - 842