Reusable XGFT interconnect IP for network-on-chip implementations

Platform-based design flows are coming into use in System-on-Chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same plafform, use also reusable interconnect IP (HP) blocks as communication infrastructures. This paper presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) HP can be used as a single large block. It is especially usable on such SoC-circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT IIP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in Network-On-Chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.