A Novel Cascaded Asymmetrical Multilevel Inverter With Reduced Number of Switches

In this article, a new cascaded multilevel inverter has been presented. In order to produce all voltage levels in output voltage waveform, eight different algorithms are proposed to determine the magnitude of dc voltage sources. This topology is able to increase the number of output voltage levels by using lower number of power electronic switches, driver circuits, power diodes, and dc voltage sources. In addition, the low amount of blocked voltage by power electronic switches is another advantage of the proposed inverter. Comparison results with other recently presented topologies in the literature are provided in terms of power electronic switches, blocking voltage, and number of dc voltage sources. Compared to other topologies, the proposed topology utilizes less number of driver circuits, insulated-gate bipolar transistors, and dc voltage sources. To approve the practicability of the proposed inverter, a prototype of the proposed topology for 57 level has been implemented. The operation and performance of the proposed topology in generating the positive and negative levels is verified through the experimental results on a 57-level inverter.